1. Field of the Invention
The present invention is generally related to latch timing circuits for integrated circuits.
2. Description of Background Art
Transparent latch timing circuits are commonly used in integrated circuits to regulate the flow of logical data signals in each logical path. Referring to FIG. 1, a common latch timing design is a two-phase non-overlapping latch timing circuit 100. During a first portion of the clock cycle, the L1 latch(es) are transparent, allowing a data input to enter the latch, such as into a logic unit 130. During the first clock phase, the L2 latch(es) are closed. During a second portion of the clock cycle, the L1 latches close and the L2 latches become transparent. The sequence of non-overlapping clock phases has several advantages. One benefit is that it prevents a race condition from occurring in outputs fed back through a second logic path 150. This makes the two-phase non-overlapping latch timing circuit robust to design shortcomings and insensitive to manufacturing factors that affect the timing of logical signals in an integrated circuit. Additionally, a two-phase non-overlapping latch timing circuit facilitates testing and debugging using a scan chain and/or other evaluation techniques.
A drawback of the conventional two-phase latch timing circuit 100 is that it consumes more clock power than desired. Some studies indicate that the clock power in a high performance microprocessor can be as high as 70% of total chip power consumption, although 30%–40% is a more typical range for a microprocessor utilizing a conventional two-phase latch timing architecture.
What is desired is a latch timing circuit that has the desirable benefits of a two-phase latch timing circuit but which also permits a reduction in clock power consumption.